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Automatic RF MESFET Amplifier
Drain-Current Controllers
ADC/DAC References
The MAX11014/MAX11015 provide an internal low-
noise +2.5V reference for the ADCs, DACs, and tem-
perature sensors. Set bits D3–D0 within the hardware
configuration register to control the source of the DAC
and ADC references. See Tables 10c and 10d.
Connect a voltage source to REFADC between +1.0V
and AV DD in external ADC reference mode. Connect a
voltage source to REFDAC between +0.7V to +2.5V in
external DAC reference mode. When using an external
voltage reference, bypass REFADC and REFDAC with
0.1μF capacitors to AGND.
Power Supplies
The MAX11014/MAX11015 operate from separate ana-
log and digital power supplies. Set the analog supply
voltage, AV DD , between +4.75V and +5.25V. Set the
digital supply voltage, DV DD , between +2.7V and
AV DD . Bypass AV DD with a 0.1μF and 1μF capacitor to
AGND and DV DD with a 0.1μF and 1μF capacitor to
DGND. The analog circuitry typically consumes 2.8mA
of supply current and the digital circuitry 3.7mA.
Set the negative analog supply voltages, AV SS and
GATEV SS , between -4.75V and -5.5V. Connect AV SS and
GATEV SS together externally. Bypass each of these neg-
ative supplies with a 0.1μF and 1μF capacitor to AGND.
The RCS_+ inputs supply the power to the input section
of the current-sense amplifiers. Set RCS_+ between
+0.5V and +11V on the MAX11014 and +5V to +32V on
the MAX11015. Bypass RCS_+ with a 0.1μF and 1μF
capacitor to AGND.
Serial Interface
The MAX11014/MAX11015 feature a pin-selectable
I 2 C/SPI serial interface. Connect SPI/ I2C to DGND to
select I 2 C mode, or connect SPI/ I2C to DV DD to select
SPI mode. SDA and SCL (I 2 C mode) and DIN, SCLK,
and CS (SPI mode) facilitate communication between
the MAX11014/MAX11015 and the master.
SPI Compatibility (SPI/ I2C = DV DD )
The MAX11014/MAX11015 communicate through a ser-
ial interface, compatible with SPI and MICROWIRE
devices. For SPI, ensure that the SPI bus master (typi-
cally a μC) runs in master mode so it generates the ser-
ial clock signal. Set the SCLK frequency to 20MHz or
less, and set the clock polarity (CPOL) and phase
(CPHA) in the μC control registers to the same value.
The MAX11014/MAX11015 operate with SCLK idling
high or low, and thus operate with CPOL = CPHA = 0 or
CPOL = CPHA = 1. Set CS low to latch input data at
DIN on the rising edge of SCLK. Output data at DOUT
is updated on the falling edge of SCLK. See Figure 1.
Temperature values are available in signed two’s-com-
plement format, while all others are in straight binary.
A high-to-low transition on CS initiates the 24-bit data
input cycle. Once CS is low, write an 8-bit command
byte (MSB first) at DIN to indicate which internal regis-
ter is being accessed. The command byte also identi-
fies whether the data to follow is to be written into the
serial interface or read out. See the Register
Descriptions section. After writing the command byte,
write two data bytes at DIN or read two data bytes at
DOUT. Keep CS low throughout the entire 24-bit word
write. The serial-interface circuitry is common to the
ADC and DAC sections.
When writing data, write an 8-bit command word and
16 data bits at DIN. See Figure 9. Data is input to the
serial interface on the rising edge of SCLK. When read-
ing data, write an 8-bit command byte at DIN and read
the following 16 data bits at DOUT. See Figure 10. Data
transitions at DOUT on the falling edge of SCLK. DIN
can be set high or low while data is being transferred
out at DOUT.
24
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